Efficient Bit-Serial Constant Multiplication for FPGAs

This paper describes how to realize place-effective synchronous bit-serial constant multiplications, which can be efficiently used for a block of constants (Multiple Constant Multiplication). The architecture combines traditional concepts and new approaches, which leads to the possibility of simultanous fast multiplications of different input values. Fast multiplications are a core for up-to-date embedded systems, as they rely on fast input processing which can be offered by common transformations. As an example, we have realized the Discrete Cosine Transformation (DCT), where we can show that our architecture features an optimal trade-off between area and speed.